The Peripheral Component Interface (PCI) is used in personal computers as an interface between the central processing unit (CPU) and various peripheral components such as VGA controllers, and the like. The PCI-X 2.0 DDR provides PCI technology with Double Data Rate (DDR) transfers. The original PCI bus was an unterminated transmission media mostly used in the point-to-point connections. This methodology worked well as long as the board trace length was restricted and the clock/data rates were below 100 MHz (legacy PCI systems have data rates equal to 33 MHz and 66 MHz). The signal integrity deteriorates rapidly in data transmission systems utilizing the unterminated transmission lines. The mismatch between the transmission line characteristic impedance and the load impedance (in this case the load impedance is an open circuit) will cause the signal reflections and negatively affect the signal integrity.
Future generations of PCI, such as PCI-X DDR, will increase the data rates to frequencies (f) of 133 MHz and beyond. Shorter signal periods (T=1/f) will not allow sufficient time for the signal overshoot/undershoot and ringing to settle out. Even with short transmission lines (board traces) the reflections must be minimized and controlled by proper line termination. Use of external line termination is unacceptable for a number of reasons. First, external termination is costly, incurring additional component, assembly labor and board area costs. Further, signal integrity is degraded due to the added external devices and trace parasitics. Moreover, the terminator must be made switchable, i.e. must be turned off, when the direction of data transfer is reversed.
The addition of an on-chip terminator costs an unacceptable silicon area penalty. The PCI-X DDR transceivers are located on the silicon chip periphery, called pads. The PCI-X DDR driver consumes the largest portion of the pad due to large MOSFET output devices. The addition of another large MOSFET device for implementation of the discrete terminator will consume a large amount of additional pad silicon area and will increase the PCI pad parasitic capacitance which is harmful to the signal integrity.
FIG. 1 illustrates a typical PCI-X system 100. As shown in FIG. 1, data transfer is from the PCI1 block 102 to the PCI2 block 104. The driver DX1 106 is enabled to drive the transmission line X1 108 such as PC board trace. The transmission line X1 108 far-end terminal X1out 110 is connected to the input of the enabled receiver RX2 112. The receiver RX1 114 and the driver DX2 116 are disabled during this data transmission.
For high signal integrity, it is desirable to have the driver DX1 106 output impedance Zout equal to the transmission line characteristic impedance Zo, i.e. Zout=Zo. Thus, it is desirable to have the input impedance Zin of the receiver RX2 112 also equal to the transmission line characteristic impedance Zo, i.e. ZIN=Zo. In the embodiment shown in FIG. 1, the input impedance ZIN of receiver RX2 116 is many orders of magnitude higher than the characteristic impedance Zo of the transmission line, i.e. ZIN>>Zo. In existing PCI systems no termination is used at the far end of the transmission line. This results in impedance mismatch for the unterminated transmission line. Consequently, signal reflections will cause severe distortions to the signal and negatively affect the reliability of data transmission.
During the mode of transmission described, the far end driver DX2 116 is tri-stated, idle, while the receiver RX2 112 is receiving the incoming data stream. The present invention employs the unused driver DX2 devices 116 for the purpose of implementation of proper far end transmission line termination.